Each PE executes strictly one instruction for each transition. Each PE is based on the micro-architecture demonstrated in previous sections and using Virtex Xilinx family. As shown in Figure 6, the pipelined architecture is built using N units of identical processing elements (PE). A maximum combined path delay of 18.152 ns. The Memory Unit chip: Maximum period: 11.892 ns at a maximum frequency of 84.090 MHz. A maximum combined path delay of 7.617 ns. The Processor chip: Maximum period: 56.371 ns at a maximum frequency of 17.740 MHz. Using Virtex Xilinx family, and performing the necessary implementation steps, we obtained the following timing reports: 1. Figure 4 and 5 were obtained using Xilinx CAD workstation. Figure 5 displays the simulation result of one round of the RC5 encryption algorithm.
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